This invention relates to semiconductor memory devices and, more particularly, to field-effect transistor circuitry for using the supply and the reference voltages to switch a voltage higher than the supply voltage and to switch a negative voltage. Circuitry for shifting such positive and negative voltages is used, for example, in the row-line driver circuits of nonvolatile memory arrays, such as electrically-erasable, electrically-programmable, read-only-memory (EEPROM) arrays.
An EEPROM memory cell typically comprises a floating-gate field-effect transistor. The floating-gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a predetermined voltage is applied to the control gate. The nonconductive state is read by a sense amplifier as a "zero" bit. The floating-gate of a non-programmed cell is neutrally charged (or slightly positively or negatively charged) such that the source-drain path under the non-programmed floating gate is conductive when the predetermined voltage is applied to the control gate. The conductive state is read by a sense amplifier as a "one" bit.
Each column and row of an EEPROM array may contain thousands of floating-gate memory cells. The sources of each cell in a column are connected to a source-column line and the source-column line for a selected cell may be connected to reference potential or ground during reading of the selected cell by a sense amplifier. The drains of each cell in a column are connected to a separate bitline (drain-column line). The control gates of each cell in a row are connected to a row line. The row line for a selected cell is connected by a row-line driver circuit to a voltage more positive than the supply voltage during programming of that cell. The row line for a selected cell is connected to a negative voltage during erasing of that cell.
Field-effect transistor technology allows the generation of a negative voltage with respect to the circuit ground by using a voltage-multiplying technique. In the conventional field-effect transistor processes, charge-pump circuits use only P-channel-type devices due to the necessity for insulating the generated negative voltage from the substrate, which is generally tied to the circuit ground. Also, no N-channel-type transistors can be used in the negative voltage path since the N+/P- junction between the transistor source or drain and the substrate would be forward-biased for direct conduction, thus shorting the negative voltage to reference voltage Vss.
This fact has limited negative-voltage charge-pump applications to those applications in which bulk-type negative biasing is used.
Previously, circuits, such as memory row-decoders, have been developed to switch a negative voltage. However, the implementation of those circuits has been difficult for a number of reasons. One of those reasons is a requirement for P-channel-type depletion transistors. In other such circuits, a separate negative charge pump must be implemented for each node of the circuit, requiring an independent selection means for each charge pump. And in other such circuits, use of silicon-on-insulator technology is required. Where such circuits use P-channel-type only circuitry, a more negative voltage is required to control the switching.
Recent advances in semiconductor processes have resulted in the availability of a deep N- tank process for implementing high-power field-effect transistors.
There is a need for a field-effect-transistor inverter-level-shifter that functions to select and to switch a voltage Vp higher than supply voltage Vdd and a voltage Vn lower than reference voltage Vss.